Digital circuits are often tested using algorithmically generated test patterns that utilize scan chains to provide stimulus to, and capture responses from, the circuits. Scan-based testing can be a cost effective method to achieve good test coverage with acceptable test time and pattern development overhead.
One concern of scan-based diagnostics can be the shifting of data through the scan chains. The amount of area on a die consumed by the scan flops, scan chain connections, and scan control circuitry can range from 15-30% or more of the die area. Thus, faults in the scan chains themselves are desirably tested through scan chain test and diagnosed through scan chain diagnosis. One concern with scan chain diagnosis, however, is the number of failure cycles that are recorded during diagnosis. For example, for a given chain pattern or scan pattern, a chain defect can sometimes result in about 50% of the flops on a defective chain failing on automated testing equipment (ATE). If the failing flops on good chains (caused by the incorrect loading values from faulty chains) are also counted, the number of failing cycles per pattern can be large. Therefore, improved techniques and tools for properly logging failing patterns for scan chain diagnostics are desired.